A Design of Network Interface Applied to Multi-core DSP Off-chip Extension

FANG Xing-fu; LIANG Li-ping

Chinese

您当前的位置：

首页 >

文章列表页 >

A Design of Network Interface Applied to Multi-core DSP Off-chip Extension

更新时间：2026-09-04

- A Design of Network Interface Applied to Multi-core DSP Off-chip Extension
- Vol. 27, Issue 5, Pages: 9-13(2010)
- 作者机构：
  
  1. 1 清华大学微电子研究所,北京,100084
  2. 2 中国科学院机构微电子学研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
移动端阅览
方幸福, 梁利平. 一种适用于多核DSP片外扩展的网络接口的设计[J]. 微电子学与计算机, 2010, 27(5): 9-13.

FANG Xing-fu, LIANG Li-ping. A Design of Network Interface Applied to Multi-core DSP Off-chip Extension[J]. 2010, 27(5): 9-13.
方幸福, 梁利平. 一种适用于多核DSP片外扩展的网络接口的设计[J]. 微电子学与计算机, 2010, 27(5): 9-13. DOI：

FANG Xing-fu, LIANG Li-ping. A Design of Network Interface Applied to Multi-core DSP Off-chip Extension[J]. 2010, 27(5): 9-13. DOI：

摘要

分析了RapidIO在多核DSP互连应用中的优势

提出了一种针对多核DSP应用的可扩展的片上网络互连结构.设计并实现了一种兼容RapidIO协议的网络接口体系结构

建立了网络接口的功能仿真模型

并在此基础上评估了网络接口的吞吐量和附加延时.

Abstract

The advantage of RapidIO in multi-core DSP interconnection is analyzed and a network on chip interconnection architecture applied for multi-core DSP application is proposed in this paper. A network interface architecture compatible of RapidIO protocol is designed and inplememented.We build up the functional simulation model of the network interface

based on which the throughput and extra time delay of the network interface is appraised.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design and implementation of network interface for network on chip and DDR3 controller

Design and Implementation of RapidIO Based Networks-on-Chip Extension Interface

Design of Network Interface Based on Mirco-code Controller

Implementation and verification of a dual-chain power gating strategy for low power design

Research on the design of blockchain-based AI-generated content traceability framework

Related Author

HAN Yujie

WEI Jinghe

JU Hu

GAO Ying

TIAN Qing

LI Qingxin

CHEN Junru

ZHAO Chun

Related Institution

The No.58 Research Institute of China Electronics Technology Group Corporation

National Key Laboratory of Integrated Circuits and Microsystems

Institute of Microelectronics, Chinese Academy of Sciences

Institute of VLSI Design, Nanjing University

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰