An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application

HUANG Xuan; CHEN Jie; ZHOU Li; LIU Zhen-yu

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An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application

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- An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application
- Vol. 27, Issue 3, Pages: 11-15(2010)
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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黄玄, 陈杰, 周莉, 刘振宇. AVS高清视频环路滤波结构与电路实现[J]. 微电子学与计算机, 2010, 27(3): 11-15.

HUANG Xuan, CHEN Jie, ZHOU Li, et al. An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application[J]. 2010, 27(3): 11-15.
黄玄, 陈杰, 周莉, 刘振宇. AVS高清视频环路滤波结构与电路实现[J]. 微电子学与计算机, 2010, 27(3): 11-15. DOI：

HUANG Xuan, CHEN Jie, ZHOU Li, et al. An Architecture and VLSI Implementation of Deblocking Filter for AVS HDTV Application[J]. 2010, 27(3): 11-15. DOI：

摘要

提出一种适用于AVS高清视频的环路滤波结构.该结构采用双端口存储器

在接收重建数据的同时

计算环路滤波结果

降低了输入输出延迟;通过改进滤波时序

达到较高的滤波效率;采用流水线计算滤波结果

提高了频率.对该模块进行了仿真和综合

在0.18m工艺下

频率为200MHz

面积为18×10等效逻辑门

支持1920×1080

每秒60帧的视频解码.

Abstract

This paper presents a novel Deblocking filter for AVS.It uses dual-port memory which receives reconstruction pixels while calculating the filter result to reduce input to output delay.It achieves high efficiency by improving timming and adopts pipeline structure to increase the frequency.Simulate this module and implement use 0.18 m

the frequency reaches 200MHz and the circuit costs 18×10 Gates

supports 1920×1080

60 frames per second video decoding.

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Related Institution

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