A High Performance Code Generator for VLIW Architectures

WANG Hong-mei; WANG Min; ZHANG Tie-jun; DAN Rui; HOU Chao-huan

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A High Performance Code Generator for VLIW Architectures

更新时间：2026-09-04

- A High Performance Code Generator for VLIW Architectures
- Vol. 27, Issue 2, Pages: 9-12(2010)
- 作者机构：
  
  1. 中国科学院机构研究生院,北京,100039
  2. 中国科学院声学研究所,北京,100190
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
移动端阅览
王红梅, 王敏, 张铁军, 单睿, 侯朝焕. 面向VLIW结构的高性能代码生成技术[J]. 微电子学与计算机, 2010, 27(2): 9-12.

WANG Hong-mei, WANG Min, ZHANG Tie-jun, et al. A High Performance Code Generator for VLIW Architectures[J]. 2010, 27(2): 9-12.
王红梅, 王敏, 张铁军, 单睿, 侯朝焕. 面向VLIW结构的高性能代码生成技术[J]. 微电子学与计算机, 2010, 27(2): 9-12. DOI：

WANG Hong-mei, WANG Min, ZHANG Tie-jun, et al. A High Performance Code Generator for VLIW Architectures[J]. 2010, 27(2): 9-12. DOI：

摘要

DSP处理器通过采用VLIW结构获得了高性能

同时也增加了编译器为其生成汇编代码的难度.代码生成器作为编译器的代码生成部件

是VLIW结构能够发挥性能的关键.由此提出并实现了一种基于可重定向编译框架的代码生成器.该代码生成器充分利用VLIW的体系结构特点

支持SIMD指令

支持谓词执行

能够生成高度指令级并行的汇编代码

显著提高应用程序的执行性能.

Abstract

VLIW architecture is used to enhance the performance of DSP

but also poses a challenge to compiler to generate efficient code for it.As code generation unit of compiler

code generator plays an important role in exploiting VLIW techniques.A code generator based on retargetable compilation infrastructure is proposed and implemented in this paper.It employs the efficient hardware in VLIW structure to greatest extend

supports both SIMD instructions and predication execution

and is able to generate high instruction-level-parallelism assembly code

which greatly improves performance of applications.

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