A High Performance,Fully Pipelined and Parameter Controllable Implementation of JPEG-LS Encoder

LIU Jia-han; ZHAO Yan; WANG Yu-xin; ZHAO Jun-suo

Chinese

您当前的位置：

首页 >

文章列表页 >

A High Performance,Fully Pipelined and Parameter Controllable Implementation of JPEG-LS Encoder

更新时间：2026-09-04

- A High Performance,Fully Pipelined and Parameter Controllable Implementation of JPEG-LS Encoder
- Vol. 27, Issue 2, Pages: 34-37(2010)
- 作者机构：
  
  1. 中国科学院机构研究生院,北京,100049
  2. 中国科学院软件研究所,北京,100190
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
移动端阅览
刘嘉晗, 赵岩, 王宇心, 赵军锁. 高性能全流水线可控参数JPEG-LS编码器实现[J]. 微电子学与计算机, 2010, 27(2): 34-37.

LIU Jia-han, ZHAO Yan, WANG Yu-xin, et al. A High Performance,Fully Pipelined and Parameter Controllable Implementation of JPEG-LS Encoder[J]. 2010, 27(2): 34-37.
刘嘉晗, 赵岩, 王宇心, 赵军锁. 高性能全流水线可控参数JPEG-LS编码器实现[J]. 微电子学与计算机, 2010, 27(2): 34-37. DOI：

LIU Jia-han, ZHAO Yan, WANG Yu-xin, et al. A High Performance,Fully Pipelined and Parameter Controllable Implementation of JPEG-LS Encoder[J]. 2010, 27(2): 34-37. DOI：

摘要

提出了一种高性能的JPEG-LS无损/近无损图像压缩算法VLSI实现结构.通过对JPEG-LS算法瓶颈的分析

针对算法中不利于流水线实现的场景缓存部分

采用了一种信号量集机制避免流水线等待.全流水线结构保证了算法实现可以满足高速图像传感器系统的吞吐量需求.同时通过高度参数化的设计

系统可以动态调整和优化算法参数

使压缩效果和效率适应不同的运行环境.算法在FPGA平台通过验证

并得到了接近甚至超过其他A-SIC实现的性能.

Abstract

A high-performance VLSI implementation of JPEG-LS algorithm for lossless/near-lossless image compression was proposed in this paper.After analyzing the bottlenecks in JPEG-LS

a semaphore collection mechanism was employed to avoid pipeline interruption in the part of context buffer.The fully-pipelined structure ensured its feasibility to high-speed image processing system

in which ultra-high-throughput is required.Benefiting from its highly-parameterized design

host systems could dynamically adjust and optimize algorithm parameters

in order to adapt compression result and efficiency to different environments.The implementation was verified on FPGA platform

and the result shows high performance that was close to or exceeding other ASIC implementation.

关键词

Keywords

references

Views

下载量

CSCD

Alert me when the article has been cited

提交

Tools

Publicity Resources

Design of a shared-memory-based spaceborne data switching architecture

The linear leastsquares positioning algorithm based on FPGA

Algorithm optimization and hardware acceleration for YOLO post processing

Optimization and implementation of FPGA-based H.264 variable block motion estimation algorithm

A secure encryption authentication system based on integrated structure of TRNG and PUF

Related Author

WANG Runze

TANG Lei

KUANG Nailiang

LIANG Yong

FENG Zhouwu

CUI Mohan

CHEN Tao

ZHU Yifei

Related Institution

Xi'an Microelectronics Technology Institute

School of Electronics and Communication Engineering, East China Normal University

School of Microelectronics, University of Science and Technology of China

西安微电子技术研究所

山西大学机构物理电子工程学院

AI问答

Postal code：100079
Tel：（010）53879206 Email：tmw@bjxintong.com.cn
Technical support is provided by Beijing Founder electronics co., LTD 京ICP备09082226号-64 京公网安备11010602201714号
It is recommended to read the content of this site in Chrome&IE9+. Please switch to extreme mode in browser 360.
Cookies We use cookies to help provide and enhance our service and tailor content. By continuing, you agree to the use of cookies.

⁰