Design of a 1.8V,10-bit,50-Ms/s Low Power Pipelined ADC[J]. 2010, 27(4): 46-49.DOI:
Design of a 1.8V,10-bit,50-Ms/s Low Power Pipelined ADC
摘要
采用每级1.5位精度的流水线结构
设计了一个10位50Ms/s的低功耗ADC.每级流水线所用的电容按比例缩小
大大地节省了功耗.同时提出了一种提高OTA压摆率的方法
进一步降低了电路的功耗
采用TSMC0.18mCMOS工艺进行设计
结果表明该ADC在输入频率20MHz、采样速率50MHz下
SNR为59dB
DNL和INL分别为±0.4和±0.5LSB
ADC的功耗为47mW.
Abstract
A 10-bit
50-Ms/s low power ADC is presented in this paper by using a pipelined architecture of 1.5bit perstage. The capacitors used in the each pipeline stage are scaled down
which results in significant power savings. Furthermore
a novel slew rate boost circuit is proposed in this paper to save the power of the OTA. The whole ADC was designed in TSMC 0.18m CMOS process. The SNR of the ADC is 59dB when the input signal frequency is 20MHz. The differential and integral non-linearity (DNL and INL) are within ±0.4 and ±0.5 LSB respectively
as well as the total power consumption is about 47mW.