Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit

CAI Min; MIN Yan-can

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Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit

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- Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit
- Vol. 27, Issue 1, Pages: 53-56(2010)
- 作者机构：
  
  华南理工大学电信学院,广东,广州,510641
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
移动端阅览
蔡敏, 闵言灿. 全流水线结构双精度浮点乘加单元的设计[J]. 微电子学与计算机, 2010, 27(1): 53-56,60.

CAI Min, MIN Yan-can. Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit[J]. 2010, 27(1): 53-56.
蔡敏, 闵言灿. 全流水线结构双精度浮点乘加单元的设计[J]. 微电子学与计算机, 2010, 27(1): 53-56,60. DOI：

CAI Min, MIN Yan-can. Design of a Fully Pipelined Double-Precision Multiply-Add-Fused Unit[J]. 2010, 27(1): 53-56. DOI：

摘要

提出了一种支持非规格化数的全流水线结构双精度浮点乘加单元 (Multiply-Add-Fused Unit

MAF

A×C+B).该乘加单元并行处理了主加法和舍入操作

解决了进位保存形式的乘法结果带来的一位误差

改进了规格化移位以便于流水线的划分.整个乘加单元划分为三级流水线

在0.13m CMOS标准单元库中

综合结果支持333 MHz的时钟频率.

Abstract

This paper presents a fully pipelined double precision MAF (Multiply Add Fused unit

A×C+B)

which accepts denormalized numbers.The unit is based on combination of the rounding with final addition

moreover

a method to deal with the one bit error from the carry saved format of multiply result is proposed

finally

the rounding architecture is improved for getting better pipeline structure.The overall MAF has a latency of 3 cycles a throughput of 1 cycle

and a frequency of 333MHz in 0.13 m CMOS technology.

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Related Institution

Xi'an Microelectronics Technology Institute

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上海交通大学电子信息与电气工程学院

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School of Information Science and Engineering, Shenyang University of Technology

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