Design and Implementation of Heterogeneous Multi-Core DSP Based on CostarⅡ

AO Tian-yong; CHEN Jie; LIU Jian; XU Han-jing; XI Jie; ZHANG Wei-feng

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Design and Implementation of Heterogeneous Multi-Core DSP Based on CostarⅡ

更新时间：2026-09-04

- Design and Implementation of Heterogeneous Multi-Core DSP Based on CostarⅡ
- Vol. 27, Issue 3, Pages: 59-62(2010)
- 作者机构：
  
  1. 1 中国科学院微电子研究所机构,北京,100029
  2. 2 河南大学机构物理与电子学院,河南,开封,475001
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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敖天勇, 陈杰, 刘建, 许汉荆, 奚杰, 张伟风. 基于CostarⅡ的异构多核DSP设计与实现[J]. 微电子学与计算机, 2010, 27(3): 59-62.

AO Tian-yong, CHEN Jie, LIU Jian, et al. Design and Implementation of Heterogeneous Multi-Core DSP Based on CostarⅡ[J]. 2010, 27(3): 59-62.
敖天勇, 陈杰, 刘建, 许汉荆, 奚杰, 张伟风. 基于CostarⅡ的异构多核DSP设计与实现[J]. 微电子学与计算机, 2010, 27(3): 59-62. DOI：

AO Tian-yong, CHEN Jie, LIU Jian, et al. Design and Implementation of Heterogeneous Multi-Core DSP Based on CostarⅡ[J]. 2010, 27(3): 59-62. DOI：

摘要

基于CostarⅡ DSP内核设计并实现了一种高性能的嵌入式异构多核DSP.该设计集成了四个DSP内核和一个RISC处理器内核;每个内核均拥有自己的私有存储器;所有内核共享具有多体并行存储结构的数据存储器;四个DSP内核使用可配置的共享程序存储器;各内核之间拥有邮箱、信号量及中断等多种同步与通信机制.为了验证该设计

在该系统上测试了JPEG解码算法

并通过了FPGA验证.测试结果表明

该设计具有编程模式简洁

易于提高任务执行的并行度的优点.

Abstract

In this paper

a high-performance heterogeneous multi-core DSP architecture is proposed and implemented based on CostarII core. The multi-core DSP architecture integrates four DSP cores and a RISC core

each core of which has its own local memory. All the cores can access data shared-memory with parallel multi-bank structure

and the four DSP cores can use program shared-memory. Furthermore

all the cores hold several synchronization and communication mechanisms

such as mailbox

semaphore and interruptions. To verify the multi-core DSP architecture

the JPEG parallel decoding is implemented in the system and verified in FPGA validation platform. The results show that the design is easy to program and efficient for parallel tasks.

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