Implementation of Scalar Multiplication Based on GF(2

CHEN Guang-hua; ZHANG Xiao-li; ZHU Jing-ming; LIU Ming

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Implementation of Scalar Multiplication Based on GF(2

更新时间：2026-09-04

- Implementation of Scalar Multiplication Based on GF(2
- Vol. 27, Issue 1, Pages: 90-93(2010)
- 作者机构：
  
  上海大学微电子研究与开发中心,上海,200072
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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陈光化, 张晓莉, 朱景明, 刘名. 基于GF（2）上椭圆曲线点乘的实现[J]. 微电子学与计算机, 2010, 27(1): 90-93,98.

CHEN Guang-hua, ZHANG Xiao-li, ZHU Jing-ming, et al. Implementation of Scalar Multiplication Based on GF(2[J]. 2010, 27(1): 90-93.
陈光化, 张晓莉, 朱景明, 刘名. 基于GF（2）上椭圆曲线点乘的实现[J]. 微电子学与计算机, 2010, 27(1): 90-93,98. DOI：

CHEN Guang-hua, ZHANG Xiao-li, ZHU Jing-ming, et al. Implementation of Scalar Multiplication Based on GF(2[J]. 2010, 27(1): 90-93. DOI：

摘要

给出了椭圆曲线加密算法的点乘实现.在实现模乘运算时

把相乘过程和模约多项式过程结合起来

以改善运算效率.片外双口RAM的使用

加快了数据存取速度

同时通过预留RAM空间

增强了系统的可扩充性.本设计用Verilog HDL语言作为设计工具

在synopsys DC Z-2007 03 solaris9工作平台上

基于chartered 0.35 CMOS的综合库

50 MHz约束下综合出结果约为18657门.

Abstract

The implemention of scalar multiplication is described in the paper. The efficiency of module multiplication is improved by the combination of the multiplication process and the reduction process. Double interface RAM is used to accelerate the speed of data access. The capability of expansion is enhanced by the reserved RAM. The scalar multiplication module is synthesized with a library of synopays DC Z - 2007 03 solaris9 0.35 CMOS- technology and the result is about 18657 gates.

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