The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor

XU Mei-hua; FAN Yu-le; LI Ke

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The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor

更新时间：2026-09-04

- The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor
- Vol. 27, Issue 7, Pages: 164-167(2010)
- 作者机构：
  
  1. 上海大学微电子研究与开发中心,上海,200072
  2. 上海大学机电工程与自动化学院,上海,200072
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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徐美华, 樊裕乐, 李科. CCD图像采集系统的低功耗流水线ADC设计[J]. 微电子学与计算机, 2010, 27(7): 164-167.

XU Mei-hua, FAN Yu-le, LI Ke. The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor[J]. 2010, 27(7): 164-167.
徐美华, 樊裕乐, 李科. CCD图像采集系统的低功耗流水线ADC设计[J]. 微电子学与计算机, 2010, 27(7): 164-167. DOI：

XU Mei-hua, FAN Yu-le, LI Ke. The Design of Low Power Dissipation Pipeline ADC in CCD Image Processor[J]. 2010, 27(7): 164-167. DOI：

摘要

设计了一个适用于面阵CCD图像采集系统的10位、90MSPS流水线ADC.通过采用低功耗动态比较器和省略输入级采样/保持模块使得该高速ADC具有低功耗的优点.电路设计使用Charter0.35m3.3V2P4M CMOS工艺.仿真结果表明:90MHz的采样速率、3.3MHz正弦信号输入下

该ADC模块具有9.3bit的有效分辨率

最大DNL为0.5LSB

最大INL为0.8LSB

整个ADC功耗仅为35.4mW.

Abstract

This paper presents design of a 10bit and 90 Ms/s pipeline ADC which is used in CCD image processor. Using Dynamic Comparator and omitting the input stage S/H (Sample and Hold)

the ADC achieved the characteristic of low-power dissipation. The designed ADC is implemented in Charter 0.35m 2P4M CMOS process technology. Simulating results indicate that it can achieve an ENOB (Effective number of bit) of 9.3 bit

a maximum DNL of 0.5 LSB

a maximum INL of 0.8 LSB for a 3.3MHz sinusoid input at 90MHz sampling rate. The total power consumption of the ADC core is only 35.4mW from a 3.3V supply.

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