Design of HW/SW Co-verification for a SoC Based on JTAG

YU Zhi-guo; WEI Jing-he

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Design of HW/SW Co-verification for a SoC Based on JTAG

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- Design of HW/SW Co-verification for a SoC Based on JTAG
- Vol. 27, Issue 10, Pages: 160-162(2010)
- 作者机构：
  
  中国电子科技集团公司第五十八研究所,江苏,无锡,214035
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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虞致国, 魏敬和. 基于JTAG的SoC软硬件协同验证平台设计[J]. 微电子学与计算机, 2010, 27(10): 160-162.

YU Zhi-guo, WEI Jing-he. Design of HW/SW Co-verification for a SoC Based on JTAG[J]. 2010, 27(10): 160-162.
虞致国, 魏敬和. 基于JTAG的SoC软硬件协同验证平台设计[J]. 微电子学与计算机, 2010, 27(10): 160-162. DOI：

YU Zhi-guo, WEI Jing-he. Design of HW/SW Co-verification for a SoC Based on JTAG[J]. 2010, 27(10): 160-162. DOI：

摘要

基于JTAG接口

提出了一种以FPGA为基础的SoC软硬件协同验证平台.在验证平台的硬件基础上

开发了调试验证软件

能够完成SRAM的读写、CF卡的读写、串口的收发、程序的下载、及程序复位等功能.利用验证平台的软硬件完成了SoC的IP模块的调试验证及操作系统μClinux的调试验证.实践表明

该验证平台有益于SoC的设计和调试

降低SoC应用系统的开发成本.

Abstract

A SoC co-verification platform based on JTAG port is presented.The hardware of platform is based on FPGA and debug software is developed on the platform.The software has some functions such as SRAM access test

CF card access test

serial port test

program download

program reset and etc.SRAM read IP module and μClinux operating system has been tested in this platform.The result indicates that the platform is beneficial to the design and the debugging of SoC.

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Related Author

DUAN Yan-liang

WEI Ting-cun

GAO Wu

XU Wang-yang

GUO De-chun

YANG Jin-xiao

CHEN Lei

ZHOU Tao

Related Institution

School of Computer, Northwestern Polytechnical University, Xi′an

1 Northwestern Polytechnical University, Xi′an

2 Beijing Microelectronics Tech.Institution

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