Design and Implementation of RTL-Based VHDL Simulator

SUN Ling-yu; LENG Ming; WEI Si-min; YANG Wei

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Design and Implementation of RTL-Based VHDL Simulator

更新时间：2026-09-04

- Design and Implementation of RTL-Based VHDL Simulator
- Vol. 27, Issue 2, Pages: 167-170(2010)
- 作者机构：
  
  1. 井冈山大学机构计算机科学系,江西,吉安,343009
  2. 上海大学计算机工程与科学学院,上海,200072
- 作者简介：
- 基金信息：
- DOI：
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- Published：2010
- 稿件说明：
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孙凌宇, 冷明, 魏斯民, 杨威. 面向RTL的VHDL语言模拟系统设计与实现[J]. 微电子学与计算机, 2010, 27(2): 167-170.

SUN Ling-yu, LENG Ming, WEI Si-min, et al. Design and Implementation of RTL-Based VHDL Simulator[J]. 2010, 27(2): 167-170.
孙凌宇, 冷明, 魏斯民, 杨威. 面向RTL的VHDL语言模拟系统设计与实现[J]. 微电子学与计算机, 2010, 27(2): 167-170. DOI：

SUN Ling-yu, LENG Ming, WEI Si-min, et al. Design and Implementation of RTL-Based VHDL Simulator[J]. 2010, 27(2): 167-170. DOI：

摘要

设计并实现了一种面向寄存器传输级的VHDL语言模拟系统 (RTL-based VHDL Simulator

RVS) .介绍了RVS系统的处理流程和组成模块.RVS系统定义了面向寄存器传输级的VHDL语言子集

在编译阶段采用了一种基于递归的自顶向下语法分析算法

在模拟阶段采用了一种具有调试功能的基于进程的事件驱动模拟调度算法.RVS系统在Windows平台下用Visual Studio2003进行了实现.实验表明

RVS系统对组合逻辑控制和微程序控制的SAP-CPU设计电路文件进行了正确地编译和模拟.

Abstract

named RVS.The RVSs flow

composition modules as well as their functions is described.Firstly

the RTL subset of VHDL language in RVS is defined.Furthermore

a top-down syntax analysis algorithm based on recursion is developed during the compilation phase.During the simulation phase

an event-driven schedule algorithm based on process is proposed with debugging functions.We give the implementation of RVS in Windows OS and Visual Studio 2003.Finally

the experiment and analysis show that the compiler and simulator of RVS perform well and produce encouraging solutions correctly on two SAP-CPU designs controlled by combinational logic and micro-program.

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