In order to improve 2-D IDCT decoding speed

a high performance Two Dimensional (2-D) Inverse Discrete Cosine Transform (IDCT) processor is proposed. The 2-D IDCT is made using 1-D IDCT

the 1-D IDCT is made using Chen algorithm

the multiply and add operation is made using distribute arithmetic. For higher decoding speed

the inputs are divided into high 6 bits and low 6 bits. The look up tables’ size is decreased by represent the inputs by (-1

1) either than (0

1). A novel method need no add operation is used for rounding. The high performance 2-D IDCT processor uses Altera EP2C20F484 FPGA and reaches an operating frequency of 165.37 MHz.