The Design of High Performance Viterbi Decoder Based on FPGA

QIU Lei; ZHANG Yan

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The Design of High Performance Viterbi Decoder Based on FPGA

更新时间：2026-09-04

- The Design of High Performance Viterbi Decoder Based on FPGA
- Vol. 27, Issue 7, Pages: 246-249(2010)
- 作者机构：
  
  哈尔滨工业大学深圳研究生院,广东,深圳,518055
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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邱磊, 张岩. 基于FPGA的高性能Viterbi译码器的设计[J]. 微电子学与计算机, 2010, 27(7): 246-249.

QIU Lei, ZHANG Yan. The Design of High Performance Viterbi Decoder Based on FPGA[J]. 2010, 27(7): 246-249.
邱磊, 张岩. 基于FPGA的高性能Viterbi译码器的设计[J]. 微电子学与计算机, 2010, 27(7): 246-249. DOI：

QIU Lei, ZHANG Yan. The Design of High Performance Viterbi Decoder Based on FPGA[J]. 2010, 27(7): 246-249. DOI：

摘要

卷积码的Viterbi译码算法已经被广泛地应用到通信和信号处理的各个领域.为了兼顾性能和面积

文中设计的(2

7)卷积码的Viterbi译码器采用串并结合的方式

对译码器的核心部分加比选单元作出了较大改进

在性能和资源的占用等方面较传统的译码器有了较大改善.

Abstract

Convolutional code and its Viterbi decoding algorithm had been widely applied to various fields of communication and signal processing. This paper presents the decoding scheme of (2

7) convolutional code. In order to take both speed and size into account

the decoder combines parallel structure with serial structure. The core part of the decoder

Add-Compare-Select Unit

has been improved greatly

and the whole decoder has the advantages of performance and resource expense than traditional Viterbi decoder.

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Related Institution

Xi'an Microelectronics Technology Institute

School of Electronics and Communication Engineering, East China Normal University

School of Microelectronics, University of Science and Technology of China

西安微电子技术研究所

山西大学机构物理电子工程学院

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