Design and Implementation of LDPC Decoder for IEEE 802.11n

ZHU Yong-xu; WU Bin; ZHANG Zhen-dong; ZHOU Yu-mei

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Design and Implementation of LDPC Decoder for IEEE 802.11n

更新时间：2026-09-04

- Design and Implementation of LDPC Decoder for IEEE 802.11n
- Vol. 28, Issue 2, Pages: 1-5(2011)
- 作者机构：
  
  中国科学院微电子研究所机构专用集成电路与系统研究室,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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朱勇旭, 吴斌, 张振东, 周玉梅. IEEE 802.11n LDPC译码的设计与实现[J]. 微电子学与计算机, 2011, 28(2): 1-5.

ZHU Yong-xu, WU Bin, ZHANG Zhen-dong, et al. Design and Implementation of LDPC Decoder for IEEE 802.11n[J]. 2011, 28(2): 1-5.
朱勇旭, 吴斌, 张振东, 周玉梅. IEEE 802.11n LDPC译码的设计与实现[J]. 微电子学与计算机, 2011, 28(2): 1-5. DOI：

ZHU Yong-xu, WU Bin, ZHANG Zhen-dong, et al. Design and Implementation of LDPC Decoder for IEEE 802.11n[J]. 2011, 28(2): 1-5. DOI：

摘要

提出了一种针对IEEE 802.11n准循环非规则LDPC译码器VLSI的设计方法.设计使用了交互信息存储器最小化设计策略

交互信息存储器与基矩阵有值点一一对应原则

最大程度减少了存储器的开销.校验节点处理采用了一种层次化偏置的最小项算法来降低复杂度

并选出合适的偏置量来提高译码器性能.采用SMIC 0.13μm CMOS工艺设计并实现了该译码器

在时钟频率为133.3 MHz时

最大数据吞吐率为100 Mb/s

功耗为73 mW.

Abstract

This paper presents a design of LDPC decoder for the irregular quasi—cyclic LDPC in IEEE802. 1ln standard. Memory minimization scheme in which the size of passing-message memory equals to the number of elements in base matrix is exploited to reduce the memory cost significantly. Offset min-sum algorithm with optimized offset parameters has been used in check node unit of stratified structure． The decoder has been implemented under SMIC 0．13μm CMOS process. The max throughput is 100 Mb／s with power of 73 mW at 1 33．3 MHz frequency.

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