Compatible AES-128、AES-192、AES-256 Serial AES Encryption and Decryption Circuit Design

HAN Shao-nan; LI Xiao-jiang

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Compatible AES-128、AES-192、AES-256 Serial AES Encryption and Decryption Circuit Design

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- Compatible AES-128、AES-192、AES-256 Serial AES Encryption and Decryption Circuit Design
- Vol. 27, Issue 11, Pages: 40-45(2010)
- 作者机构：
  
  中国科学院机构微电子研究所,浙江,杭州,310053
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2010
- 稿件说明：
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韩少男, 李晓江. 可兼容AES-128、AES-192、AES-256串行AES加密解密电路设计[J]. 微电子学与计算机, 2010, 27(11): 40-45,50.

HAN Shao-nan, LI Xiao-jiang. Compatible AES-128、AES-192、AES-256 Serial AES Encryption and Decryption Circuit Design[J]. 2010, 27(11): 40-45.
韩少男, 李晓江. 可兼容AES-128、AES-192、AES-256串行AES加密解密电路设计[J]. 微电子学与计算机, 2010, 27(11): 40-45,50. DOI：

HAN Shao-nan, LI Xiao-jiang. Compatible AES-128、AES-192、AES-256 Serial AES Encryption and Decryption Circuit Design[J]. 2010, 27(11): 40-45. DOI：

摘要

通过分析AES算法的基本原理

对算法中的AES-128、AES-192、AES-256三种不同的加密解密模式进行了综合设计

有效地利用了公共模块

与单个分别实施各个加密解密模式相比

大大减少了硬件电路面积.针对目前AES实现方法中的key产生模块进行了理论分析

提出了一种新的实现电路结构.设计出的串行AES硬件加密解密电路经综合后得到的芯片面积为31 286门

最高工作频率为66MHz

可以满足目前的大部分无线传感网络的数据交换速率的需求.

Abstract

This paper

by analyzing the basic principles of AES algorithm

integrating AES-128

AES-l92

AES-256 into a single design

which effectively uses the public modules and greatly reduces the chips area compared with a single implementation of these modules respectively. In this paper

through the analysis of the current implementation of KEY in AES algorithm

the author proposes a new circuit structure. And the result shows that the area of serial AES encryption and decryption circuit is only 31 286

a maximum operating frequency is 66MHz

which meets most data exchange rate demands of the current wireless sensor networks.

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