The priority encoder is an important basic circuit in digital systems. It is used to arbitrate among many requests

and choose a request with highest priority to complete coding

which indicates the position of the request with highest priority. The priority encoder proposed before introduces separate discharging path for each output

which leads many transistors and big power. This paper introduces a new priority encoder with shared discharging path

which is used to reduce the number of transistors and the power. The simulation result indicates that the average delay has been reduced 17%

and 5.4% average power reduction is achieved.