The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate

DING Guo-liang; CHANG Xiao-long; CHEN Jia-wen; WU Cui-xia

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The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate

更新时间：2026-09-04

- The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate
- Vol. 28, Issue 5, Pages: 67-70(2011)
- 作者机构：
  
  1. 1 军械工程学院计算机工程系,河北,石家庄,050003
  2. 2 河北工业大学,天津,300130
- 作者简介：
- 基金信息：
- DOI：
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- Published：2011
- 稿件说明：
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丁国良, 常小龙, 陈家文, 武翠霞. CMOS门电路电磁信息泄漏评估[J]. 微电子学与计算机, 2011, 28(5): 67-70.

DING Guo-liang, CHANG Xiao-long, CHEN Jia-wen, et al. The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate[J]. 2011, 28(5): 67-70.
丁国良, 常小龙, 陈家文, 武翠霞. CMOS门电路电磁信息泄漏评估[J]. 微电子学与计算机, 2011, 28(5): 67-70. DOI：

DING Guo-liang, CHANG Xiao-long, CHEN Jia-wen, et al. The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate[J]. 2011, 28(5): 67-70. DOI：

摘要

通过将CMOS工艺中的导线转化为电偶极子模型

提出了一种对CMOS工艺的门电路进行电磁信息泄漏评估的方法.仿真实验采用TSMC0.18μm工艺

实现了基于单轨逻辑以及SABL双轨逻辑的与非门

并用提出的评估方法对门电路的电磁信息泄漏进行评估.仿真结果表明

该评估方法能够对CMOS门电路的电磁信息泄漏程度进行量化评估

同时还表明了双轨门电路电磁信息泄漏弱于单轨门电路.

Abstract

A method of evaluating electromagnetic information leakage of the CMOS gate circuit was presented by changing the lead in CMOS technology into dipole model.The simulation adopted TSMC0.18 μm process technology

and implemented the NAND gate based single rail logic and SABL double rail logic

meanwhile

the electromagnetic information leakage was evaluated by the given method.The results showed that this method was able to quantitative evaluate the electromagnetic information leakage of the CMOS gate

and that the electromagnetic information leakage of double rail logic gate was much weaker than single logic gate.

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