In this paper

we present a 64 point FFT/IFFT processer developed primarily for the application in a OFDM based IEEE 802. 11a WLAN baseband processor. The proposed processor uses the four-parallel architecture of single butterfly to efficiently improve throughput

and requires only 63 clock cycles for a 64 points FFT/IFFT. Double PingPang architecture is proposed to perform storage of both input and output streaming data. The proposed processor not only supports the operation of FFT/IFFT in 64 points but can also config bits-width arbitrarily accord- ing to system demand. In addition

it uses Block-floating point algorithm which can improve precision of the processor

balances precision and resource. The proposed processor of 16 bits is designed in a HJTC 0. 18μm CMOS process

the core area is 0. 626 7 mm

the tape-out area is 1.35 mm×1.27 mm. At the highest clock frequency is 300 MHz

the power is 126. 17 mW.