A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit

SANG Hong-shi; ZHANG Zhi; YUAN Ya-jing; CHEN Peng

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A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit

更新时间：2026-09-04

- A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit
- Vol. 28, Issue 4, Pages: 73-75(2011)
- 作者机构：
  
  华中科技大学图像识别与人工智能研究所多谱信息处理技术国家级重点实验室,湖北,武汉,430074
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
移动端阅览
桑红石, 张志, 袁雅婧, 陈鹏. 数字集成电路物理设计阶段的低功耗技术[J]. 微电子学与计算机, 2011, 28(4): 73-75,80.

SANG Hong-shi, ZHANG Zhi, YUAN Ya-jing, et al. A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit[J]. 2011, 28(4): 73-75.
桑红石, 张志, 袁雅婧, 陈鹏. 数字集成电路物理设计阶段的低功耗技术[J]. 微电子学与计算机, 2011, 28(4): 73-75,80. DOI：

SANG Hong-shi, ZHANG Zhi, YUAN Ya-jing, et al. A Method of Reducing the CMOS Power During the Physical Design Stage of Digital Integrated Circuit[J]. 2011, 28(4): 73-75. DOI：

摘要

通过一个图像处理SoC的设计实例

着重讨论在物理设计阶段降低CMOS功耗的方法.该方法首先调整PAD摆放位置、调整宏单元摆放位置、优化电源规划

得到一个低电压压降版图

间接降低CMOS功耗;接着

通过规划开关活动率文件与设置功耗优化指令

直接降低CMOS功耗.最终实验结果表明此方法使CMOS功耗降低了10.92%.基于该设计流程的图像处理SoC已经通过ATE设备的测试

并且其功耗满足预期目标.

Abstract

The method to reduce the CMOS power during the physical design stage is disucssed in this paper

utilizing the SoC instance of an image processing design.Firstly

the placement locations of the PAD and macro cells were adjusted and the power planning was optimized.As a result

an intermediate layout with lower voltage drop is gained

which reduces the CMOS power indirectly.Secondly

the file of switching activity ratio planned and the power optimization instructions set are applied on the intermediate layout

and the CMOS power is directly reduced.Finally

simulation results show that the method has saved the power 10.92%.The SoC instance chip entity has passed the test on the ATE and the power meets the design expection.

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