Design and Simulate High Performace ASIP for PLC

ZENG Shu-ting; YANG Zhi-jia

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Design and Simulate High Performace ASIP for PLC

更新时间：2026-09-04

- Design and Simulate High Performace ASIP for PLC
- Vol. 28, Issue 7, Pages: 76-81(2011)
- 作者机构：
  
  1. 中国科学院沈阳自动化研究所工业信息学重点实验室,辽宁,沈阳,110016
  2. 中国科学院机构研究生院,北京,100039
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
移动端阅览
曾舒婷, 杨志家. 高性能PLC专用指令集处理器设计与仿真[J]. 微电子学与计算机, 2011, 28(7): 76-81.

ZENG Shu-ting, YANG Zhi-jia. Design and Simulate High Performace ASIP for PLC[J]. 2011, 28(7): 76-81.
曾舒婷, 杨志家. 高性能PLC专用指令集处理器设计与仿真[J]. 微电子学与计算机, 2011, 28(7): 76-81. DOI：

ZENG Shu-ting, YANG Zhi-jia. Design and Simulate High Performace ASIP for PLC[J]. 2011, 28(7): 76-81. DOI：

摘要

该高性能PLC专用指令集处理器采用自主设计的PLC专用指令集

符合PLC指令特征

可减少该PLC专用指令集处理器执行的指令数

并采用32位RISC体系结构加快PLC程序的执行速度.该高性能PLC专用指令集处理器采用哈佛总线结构

寄存器组采用位编址模式

位处理器可加速PLC布尔运算

功能块单元可提高功能块指令执行的精度

并采用四级流水线提高PLC指令的执行速度.现已完成了该高性能PLC专用指令集处理器的系统功能仿真

经测试仿真结果正确.

Abstract

The PLC ASIP adpots PLC special instruction set

which is consistent with the character of PLC instructions.The PLC special instruction set can reduce the number of instructions and accelerate the executing speed of PLC program by 32 bit RISC architecture.The designed architecture of the high performance ASIP for PLC adopts harvord bus architecture

the registers adopts bit addressing mode

the bit processor can accelerate bool operation

the function block unit can improve the precision of function block execution

the high performance ASIP for PLC adopts four pipelines to speed up the PLC instruction execution.The systemic functional simulation of the high performance ASIP for PLC has been finished

and the result of simulation is correct after testing.

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