A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm

LI Zi-lei; LIU Zheng-lin; HUO Wen-jie; ZOU Xue-cheng

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A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm

更新时间：2026-09-04

- A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm
- Vol. 28, Issue 4, Pages: 95-98(2011)
- 作者机构：
  
  华中科技大学电子科学与技术系,湖北,武汉,430074
- 作者简介：
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- Published：2011
- 稿件说明：
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李子磊, 刘政林, 霍文捷, 邹雪城. 高吞吐率XTS-AES加密算法的硬件实现[J]. 微电子学与计算机, 2011, 28(4): 95-98,102.

LI Zi-lei, LIU Zheng-lin, HUO Wen-jie, et al. A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm[J]. 2011, 28(4): 95-98.
李子磊, 刘政林, 霍文捷, 邹雪城. 高吞吐率XTS-AES加密算法的硬件实现[J]. 微电子学与计算机, 2011, 28(4): 95-98,102. DOI：

LI Zi-lei, LIU Zheng-lin, HUO Wen-jie, et al. A High-Throughput Hardware Implementation of XTS-AES Encryption Algorithm[J]. 2011, 28(4): 95-98. DOI：

摘要

基于XTS-AES算法提出了一种具有并行全流水结构的硬件实现方法.设计通过展开数据通路的方式

提高了吞吐率;同时还通过采用内部流水线结构优化关键路径的方式

提高了电路的时钟频率和整体工作性能.在UMC 90 nm CMOS工艺条件下

所设计的XTS-AES模块的吞吐率比目前已知XTS-AES的最高吞吐率提高了52.28%.分析结果表明

该硬件模块完全满足现阶段高速加密存储的需要.

Abstract

This paper proposes a new hardware implementation method for XTS-AES Algorithm that has a full parallel pipelined structure.The proposal scheme increases throughput by unrolling the data path.Meanwhile

it also improves the circuit clock frequency and overall performance by using inner pipelined structure to optimize the critical path.Compared with the currently known highest throughput XTS-AES implementation

the new XTS-AES module increases the throughput by 52.28% in UMC 90 nm CMOS technology.The result indicates that this hardware module fully meets the need of high-speed encrypted storage at present.

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