Design of High-esolution Comparator Applied in 14 bit SAR ADC

CHEN You-qing; HE Ming-hua

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Design of High-esolution Comparator Applied in 14 bit SAR ADC

更新时间：2026-09-04

- Design of High-esolution Comparator Applied in 14 bit SAR ADC
- Vol. 28, Issue 6, Pages: 109-112(2011)
- 作者机构：
  
  福州大学物理与信息工程学院,福建,福州,350108
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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陈幼青, 何明华. 应用于14bit SAR ADC的高精度比较器的设计[J]. 微电子学与计算机, 2011, 28(6): 109-112.

CHEN You-qing, HE Ming-hua. Design of High-esolution Comparator Applied in 14 bit SAR ADC[J]. 2011, 28(6): 109-112.
陈幼青, 何明华. 应用于14bit SAR ADC的高精度比较器的设计[J]. 微电子学与计算机, 2011, 28(6): 109-112. DOI：

CHEN You-qing, HE Ming-hua. Design of High-esolution Comparator Applied in 14 bit SAR ADC[J]. 2011, 28(6): 109-112. DOI：

摘要

基于预防大锁存理论

设计了一款带有三级前置运算放大器和latch再生电路的高精度比较器.为了实现高精度

采用了输入失调储存 (IOS) 和输出失调储存 (OOS) 级联的消失调方法

有效降低了比较器的输入失调电压.传统的比较器动态失调测试方法非常耗时

为此采用新的带负反馈网络的动态失调测试电路

从而大大提高了比较器的设计和仿真效率.Hhnec CZ6H (0.35μm) 工艺下

仿真表明

比较器能够分辨的最小信号为33.2μV

满足14 bit SAR ADC对比较器的性能要求.

Abstract

Based on preamplifier-latch theory

a high-resolution comparator with three pre-amplifiers and a latch is presented.In order to achieve high-resolution

both IOS and OOS offset cancellation technique is used

which successfully decreases the input offset voltage.The traditional dynamic offset test method is time consuming

so a new dynamic offset test bench containing a negative feedback loop is adopted

which efficiently speeds up the design and simulation.The simulation results show that comparator can distinguish 33.2 μV under hhnec CZ6H (0.35 μm) process.It is suitable for the 14 bit SAR ADC.

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Related Institution

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