您当前的位置:
首页 >
文章列表页 >
Optimization Design for IQ Coded and FPGA Verify
更新时间:2026-09-04
    • Optimization Design for IQ Coded and FPGA Verify

    • Vol. 27, Issue 12, Pages: 124-126(2010)
    • Published:2010

    移动端阅览

  • HAN Si-xiao, SHAO Bing-xian. Optimization Design for IQ Coded and FPGA Verify[J]. 2010, 27(12): 124-126. DOI:

  •  
  •  
icon
试读结束,您可以激活您的VIP账号继续阅读。
去激活 >
icon
试读结束,您可以通过登录账户,到个人中心,购买VIP会员阅读全文。
已是VIP会员?
去登录 >

0

Views

12

下载量

0

CSCD

Alert me when the article has been cited
提交
Tools
Download
Export Citation
Share
Add to favorites
Add to my album

Related Articles

Optimization and implementation of FPGA-based H.264 variable block motion estimation algorithm
Design and Implementation of HDMI High-Definition Video Editing Based on Leonardo DaVinci
Monte carlo analysis of V-layout trench SiC neutron detector
Microservices anomaly detection based on the correlation of monitoring metrics
A feature-oriented context understanding and slice analysis network for tuberculosis detection

Related Author

LI Yu
GONG Longqing
ZHAO Haiting
ZHANG Shuo
LI Bo
YANG Ting

Related Institution

Xi'an Institute of Microelectronics Technology
Key Laboratory of Instrumentation Science& Dynamic Measurement, Ministry of Education, North University of China
0