The Research of CIS Chip Wafer Level Packaging Process Based on TSV

DONG Xi-ying; XU Cheng-xiang

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The Research of CIS Chip Wafer Level Packaging Process Based on TSV

更新时间：2026-09-04

- The Research of CIS Chip Wafer Level Packaging Process Based on TSV
- Vol. 28, Issue 4, Pages: 151-155(2011)
- 作者机构：
  
  南京信息职业技术学院,江苏,南京,210046
- 作者简介：
- 基金信息：
- DOI：
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- Published：2011
- 稿件说明：
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董西英, 徐成翔. 基于TSV技术的CIS芯片晶圆级封装工艺研究[J]. 微电子学与计算机, 2011, 28(4): 151-155.

DONG Xi-ying, XU Cheng-xiang. The Research of CIS Chip Wafer Level Packaging Process Based on TSV[J]. 2011, 28(4): 151-155.
董西英, 徐成翔. 基于TSV技术的CIS芯片晶圆级封装工艺研究[J]. 微电子学与计算机, 2011, 28(4): 151-155. DOI：

DONG Xi-ying, XU Cheng-xiang. The Research of CIS Chip Wafer Level Packaging Process Based on TSV[J]. 2011, 28(4): 151-155. DOI：

摘要

基于TSV技术的封装技术是目前MEMS产品、存储器、3D IC封装中的高端和热点技术.本文论述了在国内处于领先并正在量产化研究阶段的基于TSV技术的CIS芯片晶圆级封装工艺流程.通过理论分析和实验

重点研究了在封装流程中将铝刻蚀、去胶提前到金属镀覆之前的意义和所出现的镍滋生问题.研究表明

将铝刻蚀、去胶提前到金属镀覆之前可以缩短去胶时间

减少光刻胶的残留和金属镀覆层数;通过延长金属镀覆过程中每次UPW冲洗时间

在EN Ni中防止镀液结镍

并在镀锌时降低锌液的粘附性和镀锌后增加硝酸清洗步骤

即可消除镍滋生.以上研究对于提高封装效率和合格芯片率

降低成本是很有意义的.

Abstract

TSV-based packaging technology is a kind of high-end technology currently used in MEMS

memory and three-dimensional integrated circuits.This article discusses the TSV-based CIS chip wafer level packaging process which is in the mass production phase and in a leading position in our country.The emphasis of this work focuses on the theoretical and experimental investigations of executing aluminum etching and photoresist removal before metallic coating

and the induced Ni-breeding problem.It is found that the new process flow can shorten the time of photoresist removal

decrease the residua of photoresist and reduce the number of layers of metallic coating.Extending UPW rinse time in electroplating process each time

avoiding forming Nickel particles in plating solution in EN Ni.Lowering zinc concentration when zinc plating and increase nitric acid cleaning steps therefore circumvent the problem of Ni-breeding.The results are helpful to improve the efficiency

increase the passing rate of the chips greatly and reduce the costs.

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