In the baseband signal processing chip

the area and speed are two key indicators.In this paper

we present a design which is based on the modified booth algorithm

using the Dadda tree compression algorithm with the improvement of the basic unit

while using the method of the sign bit and zero-filling of the tail to optimize the design

not only to maintain the Wallace tree structure of the advantages of parallel computing

and area also been greatly improved.Comparing to the Wallace tree structure

the rules of the structure is more conducive to layout.With compression results using a multi-CLA block technology

the multiplier′s speed is further improved.Under the SMIC 0.13μm CMOS process with the eight-layer metal

the synthesis result of this design by DC (Design Compiler) showed that the chip area is 20633.59μm

and the maximum delay is only 3.00ns.