Power block is an important part of CMOS image sensors (CIS)

and its properties affect the power consumption and the image qualities of CIS directly.In this paper

based on the configurations of the pixel and the column readout circuit

the design methodology of power block with low power consumption and programmable functions is proposed

and the circuit design using 0.18μm CMOS process is completed.The Hspice simulation results show that the stable and correct voltages can be generated in 70 ms when the system is on

and the average power consumption of power block is less than 1mW.