According to the on-line error detection requirement of embedded processors

this paper presents a parallel error detection structure of SPARC V8 architecture compatible ALU

which takes the B0 encoding of Berger code prediction as the parallel on-line error detection strategy.This structure can be integrated into the SPARC V8 architecture compatible ALU directly

and forms a parallel error detection ALU.Comparing with the two-rail logic method

this structure gets the hardware cost decrease.Comparing with pseudoduplication method

in which the same circuit successively processes data twice but along different data path

this structure has an obviously performance advantage.