Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid

YU Zeng-hui; HEI Yong; CHEN Li-ming; XU Xin-feng; WU Zhao-sheng

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Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid

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- Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid
- Vol. 29, Issue 4, Pages: 14-18(2012)
- 作者机构：
  
  1. 1 中国科学院微电子研究所机构专用集成电路与系统研究室,北京,100029
  2. 2 国民技术股份有限公司,广东,深圳,518057
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2012
- 稿件说明：
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于增辉, 黑勇, 陈黎明, 徐欣锋, 吴兆胜. 多通道数字助听器算法及低功耗VLSI设计[J]. 微电子学与计算机, 2012, 29(4): 14-18.

YU Zeng-hui, HEI Yong, CHEN Li-ming, et al. Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid[J]. 2012, 29(4): 14-18.
于增辉, 黑勇, 陈黎明, 徐欣锋, 吴兆胜. 多通道数字助听器算法及低功耗VLSI设计[J]. 微电子学与计算机, 2012, 29(4): 14-18. DOI：

YU Zeng-hui, HEI Yong, CHEN Li-ming, et al. Algorithm Research and Low-power VLSI Design of a Multi-channel Digital Hearing Aid[J]. 2012, 29(4): 14-18. DOI：

摘要

改进了多通道数字助听器中的听力补偿和噪声消除算法

并进行了低功耗VLSI设计.听力补偿方面

提出一种改进的多通道宽动态范围压缩(WDRC)算法;该方法降低了存储和计算开销

并抑制了对残余背景噪音的过度放大.噪声消除方面

利用语音谱和噪声谱的帧间相关性

改进了传统的多子带谱相减算法

使之在硬件实现时便于并行运算

同时不影响消噪性能.最后

综合采用多种低功耗设计方法

在SMIC的130nm工艺条件下

完成了基于上述算法的多通道数字助听器VLSI设计.后仿结果表明

该设计总功耗仅为228μW.

Abstract

The hearing compensation algorithm and noise reduction algorithm in multi-channel digital hearing aids were studied in this paper

and a low-power VLSI design according to these algorithms was implemented further.On hearing compensation

a new multi-channel Wide Dynamic Range Compression(WDRC) algorithm was proposed

which can not only reduce the cost of storage and calculation.On noise reduction

by considering the correlation between adjacent frames of speech spectrum and noise spectrum

the traditional multi-band spectral subtraction algorithm was modified for parallel operation in hardware implementation

without degrading the performance.The low-power VLSI design of a multi-channel digital hearing aid based on the proposed algorithms was realized in SMIC 130nm process.The post-simulation power dissipation of the system is only 228 μW.

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Related Institution

Institute of Microelectronics, Chinese Academy of Sciences

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