Design of FPGA-based 16-bit Stack Processor

CHU Zhao-xian; SHI Hui-bin

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Design of FPGA-based 16-bit Stack Processor

更新时间：2026-09-04

- Design of FPGA-based 16-bit Stack Processor
- Vol. 29, Issue 2, Pages: 22-26(2012)
- 作者机构：
  
  南京航空航天大学计算机科学与技术学院,江苏,南京,210016
- 作者简介：
- 基金信息：
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- Published：2012
- 稿件说明：
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储昭贤, 施慧彬. 基于FPGA的16位堆栈处理器的设计[J]. 微电子学与计算机, 2012, 29(2): 22-26.

CHU Zhao-xian, SHI Hui-bin. Design of FPGA-based 16-bit Stack Processor[J]. 2012, 29(2): 22-26.
储昭贤, 施慧彬. 基于FPGA的16位堆栈处理器的设计[J]. 微电子学与计算机, 2012, 29(2): 22-26. DOI：

CHU Zhao-xian, SHI Hui-bin. Design of FPGA-based 16-bit Stack Processor[J]. 2012, 29(2): 22-26. DOI：

摘要

设计了一款面向嵌入式控制领域的16位堆栈处理器

该处理器包含两个堆栈:执行数学表达式的数据堆栈和支持子程序调用的返回堆栈

其指令集含35条堆栈指令.详细给出了该堆栈处理器的体系结构及设计方法;不仅采用简单有效的指令编码方式缩小了代码体积

同时给出了单周期操作多个堆栈元素的解决方法.该处理器采用FPGA实现

在XC5VLX110T芯片上的运行时钟频率最高达到146.7MHz.最后给出了设计的软件仿真与硬件综合结果.

Abstract

This paper introduces a 16-bit stack processor for embedded control.The stack processor has two stacks: a data stack for evaluating mathematical expression and a return stack for calling subroutine.The instruction set includes 35 stack instructions.The architecture and design of the stack processor are presented.Not only a simple and effective instruction encoding is adopted to reduce the code size

but also the method to operate multiple stack elements in a single cycle is proposed.The processor is implemented by FPGA.Finally

the results of software simulation and hardware synthesizing are presented

and it comes out that the processor is able to run up to 146.7MHz on XC5VLX110T.

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