Design of pipeline without translation from CISC instructions to RISC instructions.Instruction buffers and caches are implemented in the front stage of CISC pipeline with double Program Counters pointing to opcode and operand separately.Multi-port registers and memories are designed to support simultaneously read and write by different stages.Optimization for pipeline functions is adopted in order to realize an effective CISC pipeline system.Final evaluation and test by ModelSim and Xilinx tool sets prove the design workable and preferable.