This paper proposes a full asynchronous design flow based on Balsa and Xilinx FPGA for asynchronous circuit design tools.The asynchronous circuit is described in the Balsa language to generate corresponding net list file

and a configurable file can be obtained by importing the netlist into Xilinx FPGA.With downloading the configurable file into FPGA chip

the board-level verification and post-place % route are achieved.Thus

both asynchronous design and verification in synchronous EDA software contact successfully.Finally

the feasibility of the asynchronous design flow has been proved by the design example of 8-bits asynchronous full-adder.