With the SPICE simulation of the PLL

in order to ensure the simulation accuracy

the time step need to set very small

which gives rise to large amount of data and very long simulation time.And in the early design stage

very accurate results are often not needed.Therefore

in order to improve design efficiency of ADPLL (all-digital phase-locked loop)

it is necessary to establish an efficient simulation model.A new ADPLL simulation model based on hardware description language is proposed

which shorten the time spent on system-level architecture and algorithm-level Behavior verification.