Design of a Current-Mode Sample-and-Hold Circuit Based on CCCⅡ

LI Zhan; WANG Chun-hua; PENG Guan-chao; WANG Hui-jie

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Design of a Current-Mode Sample-and-Hold Circuit Based on CCCⅡ

更新时间：2026-09-04

- Design of a Current-Mode Sample-and-Hold Circuit Based on CCCⅡ
- Vol. 28, Issue 9, Pages: 55-58(2011)
- 作者机构：
  
  湖南大学计算机与通信学院,湖南,长沙,410082
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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李湛, 王春华, 彭关超, 王会杰. 基于新颖CCCⅡ的电流模式采样保持电路设计[J]. 微电子学与计算机, 2011, 28(9): 55-58.

LI Zhan, WANG Chun-hua, PENG Guan-chao, et al. Design of a Current-Mode Sample-and-Hold Circuit Based on CCCⅡ[J]. 2011, 28(9): 55-58.
李湛, 王春华, 彭关超, 王会杰. 基于新颖CCCⅡ的电流模式采样保持电路设计[J]. 微电子学与计算机, 2011, 28(9): 55-58. DOI：

LI Zhan, WANG Chun-hua, PENG Guan-chao, et al. Design of a Current-Mode Sample-and-Hold Circuit Based on CCCⅡ[J]. 2011, 28(9): 55-58. DOI：

摘要

设计了一种新颖的第二代电流控制电流传输器 (CCCⅡ).该模块电路采用了CMOS复合管构成的跨导线性环结构

并通过外加偏置电流I的方法来控制CCCⅡ X端的寄生电阻R.当偏置电流源I=10μA时

X端的寄生电阻R=2.16kΩ

与理论值的误差只有1.32%.基于提出的CCCⅡ实现了一种电流模式的采样保持电路.基于TSMC 0.18μm CMOS工艺

采样时钟频率为100MHz时

该采样保持电路对正弦电流信号采样保持有着很高的采样精度

其正确性通过PSPICE的仿真结果得以验证.

Abstract

This paper proposed a novel current controlled second generation current conveyor (CCCⅡ).The CCCⅡ is based on translinear loop of compound CMOS transistors

which adjust the parasitic resistance with the outside biasing current I.When the biasing current I is 10 μA

the parasitic resistance of terminal X is 2.16 kΩ.The error compared with the theoretical value is only 1.32%.Based on this CCCⅡ

a current mode sample-and-hold circuit is proposed.When the frequency of the sampling clock signal is 100 MHz

the circuit can achieve excellent sampling accuracy in TSMC 0.18 μm CMOS process.The working principle of the circuit is discussed

and the simulation results confirm the theory analysis.

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