BISR is to achieve the internal nature of the automatic correction function.In order to supervise SRAMs 176-bit wide parallel data

this paper proposed a method to optimize the BISR which based on extended hamming code.The data has been split into two parts suit for ECC architecture.Under the exchangeable logic terms

we built a Signature-map for XOR-Tree.In TSMC 90nm process the results met the project requirements showing reduced 28% of delay

35% of area and 36% of power.At last

ECC delay is 1.5 ns

area

6 200 m and power dissipation

0.54 mW.These data demonstrate the effectiveness of our optimal method.