The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design

OUYANG Zhong-ming; SHAO Zhi-biao; YAO Jian-feng; ZHANG Guo-guang

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The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design

更新时间：2026-09-04

- The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design
- Vol. 28, Issue 9, Pages: 131-134(2011)
- 作者机构：
  
  1. 1 西安交通大学电信学院,陕西,西安,710049
  2. 2 佛山蓝箭电子有限公司,广东,佛山,528000
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2011
- 稿件说明：
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欧阳忠明, 邵志标, 姚剑峰, 张国光. 高速ADC中折叠电路的改进[J]. 微电子学与计算机, 2011, 28(9): 131-134.

OUYANG Zhong-ming, SHAO Zhi-biao, YAO Jian-feng, et al. The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design[J]. 2011, 28(9): 131-134.
欧阳忠明, 邵志标, 姚剑峰, 张国光. 高速ADC中折叠电路的改进[J]. 微电子学与计算机, 2011, 28(9): 131-134. DOI：

OUYANG Zhong-ming, SHAO Zhi-biao, YAO Jian-feng, et al. The Modifying of Folding Circuit in High-Speed A/D Converter Chip Design[J]. 2011, 28(9): 131-134. DOI：

摘要

针对8bit 125Ms/s折叠插值A/D转换器芯片设计

文中提出了一种新的折叠波产生算法

在低压设计中节省了电压设计余度.折叠电路的尾电流源采用低压宽摆幅的共源共栅结构

使差分对的尾电流源更匹配

改善了整个A/D转换器的非线性;折叠电路输出端采用跨阻放大器输出

提高了折叠电路输出端的带宽;采用共模反馈电路

使折叠输出的共模点更稳定

减小了折叠波的过零点失真.整个电路采用2.5V低电压设计

UMC 0.25μm的工艺模型参数

用Hspice对A/D电路进行模拟验证.结果表明

此电路取得了预期结果.

Abstract

In the 8bit 125MHz Sample/s folding and interpolating A/D converter chip design

one new method of folding waves production is put forward

which economize the voltage assignment in low-voltage analog design.The wide-swing Cascode topology is used in the tail currents design

which makes the tail currents of differential pairs match better

so DNL and INL of A/D convert system is reduced.A trans-resistance amplifier is used in the output nodes of folding circuit

which increase the analog bandwidth.The CMFB topology makes the common-mode level of output voltage more stable

which decreases zero-crossing distortion.In this project

VDD is 2.5V.The whole A/D system is simulated and validated in Hspice

and the simulation environment is 0.25μm CMOS process of UMC.

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