Design of a Flip-flop with Power Failure Data Retention

ZHANG Yi-yun; CHEN Hou-peng; WANG Qian; XU Wei-yi; JIN Rong; SONG Zhi-tang

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Design of a Flip-flop with Power Failure Data Retention

更新时间：2026-09-04

- Design of a Flip-flop with Power Failure Data Retention
- Vol. 29, Issue 7, Pages: 4-7(2012)
- 作者机构：
  
  中国科学院上海微系统与信息技术研究所, 信息功能材料国家重点实验室机构 , 纳米技术研究室,上海,200050
- 作者简介：
- 基金信息：
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- Published：2012
- 稿件说明：
移动端阅览
张怡云, 陈后鹏, 王倩, 许伟义, 金荣, 宋志棠. 一种具有掉电数据保持功能的触发器设计[J]. 微电子学与计算机, 2012, 29(7): 4-7.

ZHANG Yi-yun, CHEN Hou-peng, WANG Qian, et al. Design of a Flip-flop with Power Failure Data Retention[J]. 2012, 29(7): 4-7.
张怡云, 陈后鹏, 王倩, 许伟义, 金荣, 宋志棠. 一种具有掉电数据保持功能的触发器设计[J]. 微电子学与计算机, 2012, 29(7): 4-7. DOI：

ZHANG Yi-yun, CHEN Hou-peng, WANG Qian, et al. Design of a Flip-flop with Power Failure Data Retention[J]. 2012, 29(7): 4-7. DOI：

摘要

提出了一种用相变器件作为可擦写存储单元的具有掉电数据保持功能的触发器电路.该触发器由四部分组成:具有恢复掉电时数据的双置位端触发器DFF、上电掉电监测置位电路(Power On/Off Reset)、相变存储单元的读写电路(Read Write)和Reset/Set信号产生电路

使之在掉电时能够保存数据

并在上电时完成数据恢复.基于0.13μm SMIC标准CMOS工艺

采用Candence软件对触发器进行仿真

掉电速度达到0.15μs/V的情况下

上电时可以在30ns内恢复掉电时的数据状态.

Abstract

A flip-flop with power failure data retention

using phase change material as rewritable storage units

is proposed.The flip-flop consists of four parts: a double set DFF with the function of power failure data retention

power on/off detector

read and write circuit of phase-change memory cell and Reset/Set signal generator.So that data can be saved when power is off and recovered when power is on.Based on 0.13 μm SMIC static CMOS process

the flip-flop is simulated in Candence.Under the condition of 0.15 μs/V power-down speed

data can be recovered in 30ns after power up.

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