To considerably satisfy the requirement

a high speed double precision floating point multiplier based on FPGA is presented.The proposed design adopted radix-4 Booth coder to obtain partial products

then an optimal Wallace tree compression architecture is exploited on these partial products to get a pseudo-sum and pseudo-carry

which are partially accumulated in a parallel approach to generate mantissa of the product.The design with 5-stage pipeline architecture can achieve 123.32MHz targeted at a Cyclone Ⅱ EP2C35F672C6 device.By taking the same optimization efforts

the design gets 11% enhancement on operating frequency over an Altera IP core using DSP multipliers

while about 67% over such IP core without using DSP multipliers.