Analysis and Design of High Speed Comparator Using 0.18μm SiGe BiCMOS Process

CHEN Tian-zuo; WU Yu-ping; CHEN Lan

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Analysis and Design of High Speed Comparator Using 0.18μm SiGe BiCMOS Process

更新时间：2026-09-04

- Analysis and Design of High Speed Comparator Using 0.18μm SiGe BiCMOS Process
- Vol. 29, Issue 7, Pages: 51-54(2012)
- 作者机构：
  
  中国科学院微电子研究所机构,北京,100029
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2012
- 稿件说明：
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陈天佐, 吴玉平, 陈岚. 基于0.18μm SiGe BiCMOS工艺的高速比较器分析与设计[J]. 微电子学与计算机, 2012, 29(7): 51-54.

CHEN Tian-zuo, WU Yu-ping, CHEN Lan. Analysis and Design of High Speed Comparator Using 0.18μm SiGe BiCMOS Process[J]. 2012, 29(7): 51-54.
陈天佐, 吴玉平, 陈岚. 基于0.18μm SiGe BiCMOS工艺的高速比较器分析与设计[J]. 微电子学与计算机, 2012, 29(7): 51-54. DOI：

CHEN Tian-zuo, WU Yu-ping, CHEN Lan. Analysis and Design of High Speed Comparator Using 0.18μm SiGe BiCMOS Process[J]. 2012, 29(7): 51-54. DOI：

摘要

基于预放大正反馈锁存比较理论

给出了一种8bit 8Gs/s高速比较器的设计.该比较器采用预放大器结构以提高分辨率、加快比较过程

采用主从锁存器降低亚稳态发生概率

采用输出缓冲器改善输出波形、提供测试接口;在HHNEC 0.18μm SiGe BiCMOS工艺下

采用Cadence Spectre进行仿真

结果显示

该比较器精度为4mV

输出摆幅±300mV

锁存时间37ps

过驱动恢复时间22ps

功耗约57mW

表现出良好的性能.

Abstract

A high speed comparator is presented in this paper

which is designed based on the theories of pre-amplifier and positive feedback.This comparator consists of a preamplifier

a master-slave latch

and an output buffer

to improve the resolution and decrease the occurrence probability of metastability.The comparator is fabricated in HHNEC 0.18μm SiGe BiCMOS process and is simulated using Cadence Spectre.The simulation results show that the resolution of the comparator is 4mV

and the differential output voltage swing is±300mV.The latch time and the recovery time of the comparator are relatively 37ps and 22ps

with about 57mW power consumption.

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