The Design of MOS Current Mode Logic Frequency Divider

LIANG Bei; MA Kui; FU Xing-hua

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The Design of MOS Current Mode Logic Frequency Divider

更新时间：2026-09-04

- The Design of MOS Current Mode Logic Frequency Divider
- Vol. 29, Issue 10, Pages: 157-160(2012)
- 作者机构：
  
  1. 贵州大学科技学院,贵州,贵阳,550025
  2. 贵州大学微纳电子技术重点实验室,贵州,贵阳,550025
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2012
- 稿件说明：
移动端阅览
梁蓓, 马奎, 傅兴华. MOS电流模逻辑分频器设计[J]. 微电子学与计算机, 2012, 29(10): 157-160,165.

LIANG Bei, MA Kui, FU Xing-hua. The Design of MOS Current Mode Logic Frequency Divider[J]. 2012, 29(10): 157-160.
梁蓓, 马奎, 傅兴华. MOS电流模逻辑分频器设计[J]. 微电子学与计算机, 2012, 29(10): 157-160,165. DOI：

LIANG Bei, MA Kui, FU Xing-hua. The Design of MOS Current Mode Logic Frequency Divider[J]. 2012, 29(10): 157-160. DOI：

摘要

用参数已经优化的MCML (MOS电流模逻辑)电路设计了锁存器

对锁存器的功耗及延迟进行了仿真分析;基于该锁存器分别设计了一个二分频和四分频电路

二分频电路的最高工作频率达到7.7GHz.四分频电路采用两个二分频电路直接级联

由于无缓冲连接

不仅减小了第一级的输出节点电容

同时减小了芯片的面积.电路仿真均在SMIC 0.13μmCMOS工艺下完成.

Abstract

The MCML (MOS current mode logic) latch is designed with optimized parameters.Its power consumptionand delay is analyzed and simulated.Based on this latches

the 1:2 and the 1:4 frequency divider is designed

respectively.The maximum operating frequency of the 1:2 frequency divider is 7.7 GHz.The 1:4 frequency divider has be realized by two 1:2 frequency dividers in cascade.Without buffers

the 1:4 frequency divider reduce the first stage output node capa-citance

and reduce the area of the chips.Circuits were simulated in the SMIC 0.13μm CMOS technology.

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