Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS

GONG Yan-gang; LIANG Yong-jie; LIU Cun-sheng; SUN You-min

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Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS

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- Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS
- Vol. 30, Issue 4, Pages: 156-159(2013)
- 作者机构：
  
  西安微电子技术研究所,陕西,西安,710054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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公衍刚, 梁永杰, 刘存生, 孙有民. 0.35μm CMOS多晶硅栅刻蚀工艺研究[J]. 微电子学与计算机, 2013, 30(4): 156-159.

GONG Yan-gang, LIANG Yong-jie, LIU Cun-sheng, et al. Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS[J]. 2013, 30(4): 156-159.
公衍刚, 梁永杰, 刘存生, 孙有民. 0.35μm CMOS多晶硅栅刻蚀工艺研究[J]. 微电子学与计算机, 2013, 30(4): 156-159. DOI：

GONG Yan-gang, LIANG Yong-jie, LIU Cun-sheng, et al. Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS[J]. 2013, 30(4): 156-159. DOI：

摘要

本文主要研究0.35m CMOS多晶硅栅刻蚀工艺中“硅LOSS”及“T腰”问题的形成机理.在不改变产品工艺流程的前提下

对多晶硅栅刻蚀工艺进行优化

提出“两步ME法”优化了刻蚀形貌

改善了硅LOSS、T腰的问题.满足0.35m CMOS多晶形貌及工艺要求

具有一定的理论指导和实际意义.

Abstract

Poly-silicon gate etching process based on the 0.35m CMOS was studied in detail

and the formation mechanism of silicon loss and profile T on the sidewall was investigated in this paper.Moreover

the paper optimized the etch process and finally found the "two procedures of Main Etch" method to solve the problems of silicon loss and profile T

by not changing other process conditions of CMOS.The result is accorded with the 0.35m CMOS process specification very well.The paper has the theoretical direction and practical value.

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