A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point

ZHANG Yi; YUAN Zhu; LUO Jin-xuan

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A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point

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- A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point
- Vol. 29, Issue 8, Pages: 179-184(2012)
- 作者机构：
  
  电子科技大学电子科学技术研究院机构,四川,成都,611731
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2012
- 稿件说明：
移动端阅览
张益, 袁著, 罗金选. 一种新型的定点到浮点转换的全流水线FPGA实现[J]. 微电子学与计算机, 2012, 29(8): 179-184.

ZHANG Yi, YUAN Zhu, LUO Jin-xuan. A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point[J]. 2012, 29(8): 179-184.
张益, 袁著, 罗金选. 一种新型的定点到浮点转换的全流水线FPGA实现[J]. 微电子学与计算机, 2012, 29(8): 179-184. DOI：

ZHANG Yi, YUAN Zhu, LUO Jin-xuan. A New FPGA Realization of the Full-Pipeline of Conversion from Fixed-point to Floating Point[J]. 2012, 29(8): 179-184. DOI：

摘要

利用FPGA器件完全采用底层自主设计

实现定点数到浮点数的转换.提出了一种全新的实现方法

变对数为减法

通过占用1%的逻辑资源

实现3个时钟周期输出数据.避免了局限于使用IP core的束缚

为后续ASIC设计打下了基础.

Abstract

In this paper

completely independent and bottom-level design is conducted by utilizing FPGA device

realizing conversion from fixed-point to floating point. A completely new method is proposed for such realization to output data by taking 3 clock cycles. In this method

subtraction calculation instead of logarithm calculation is adopted

occupying 1 % logic resources and avoiding the restrictions of using IP core and laying a foundation for follow-up ASIC design.

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Related Institution

Xi'an Microelectronics Technology Institute

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