VLSI Design of 2D IDCT Architecture for HEVC

CHEN Shuangshuang; HONG Liang; HE Weifeng; MAO Zhigang

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VLSI Design of 2D IDCT Architecture for HEVC

更新时间：2026-09-04

- VLSI Design of 2D IDCT Architecture for HEVC
- Vol. 30, Issue 7, Pages: 55-59(2013)
- 作者机构：
  
  上海交通大学微电子学院,上海,200240
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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陈双双, 洪亮, 何卫锋, 毛志刚. 基于HEVC的IDCT变换的VLSI设计与实现[J]. 微电子学与计算机, 2013, 30(7): 55-59.

CHEN Shuangshuang, HONG Liang, HE Weifeng, et al. VLSI Design of 2D IDCT Architecture for HEVC[J]. 2013, 30(7): 55-59.
陈双双, 洪亮, 何卫锋, 毛志刚. 基于HEVC的IDCT变换的VLSI设计与实现[J]. 微电子学与计算机, 2013, 30(7): 55-59. DOI：

CHEN Shuangshuang, HONG Liang, HE Weifeng, et al. VLSI Design of 2D IDCT Architecture for HEVC[J]. 2013, 30(7): 55-59. DOI：

摘要

HEVC(High Efficient Video Coding)是继 H.264/AVC之后正在研发的新一代视频编码标准.与之前的视频编码标准不同的是，HEVC提出了不同尺寸的变换编码单元来进行图像的空间冗余压缩.本文设计了一种面向HEVC的32点二维IDCT的全流水电路结构.为了减少I/O带宽压力和硬件开销，电路采用了单端口输入输出、蝶形运算展开以及奇偶分离累加的方法.在 TSMC90nm工艺下综合得到该电路最快工作频率为315M Hz，电路总门数为47K.仿真结果显示该电路结构可以在300M Hz频率下对分辨率为4096×2048的超高清视频做30帧/秒的32点IDCT解码.

Abstract

High Efficiency Video Coding (HEVC) is the currently developing video coding standard beyond H.264/AVC.Differing from previous video codec standards

HEVC proposes the variable block size Transform Unit (TU) to conduct spatial redundancy compression.In this paper

a novel fully pipelined 2 -D 32×32 IDCT architecture based on HEVC is presented.To reduce the I/O peak bandwidth and hardware overhead

single -port I/O

the butterfly unrolling and the Odd/Even accumulation separation method is adopted.Using TSMC90nm technology

the proposed architecture is implemented with the maximum work frequency at 315M Hz with 47K Gates.Simulation results show that the proposed architecture is able to process 4096×2048@30fps image with 32×32 IDCT.

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Related Institution

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