A Method Based on Configurable Random Test Generation for Multi-core Verification

LUO Han-qing; LIANG Li-ping; YE Tian-chun

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A Method Based on Configurable Random Test Generation for Multi-core Verification

更新时间：2026-09-04

- A Method Based on Configurable Random Test Generation for Multi-core Verification
- Vol. 31, Issue 1, Pages: 88-91(2014)
- 作者机构：
  
  中国科学院机构微电子研究所,北京,100029
- 作者简介：
- 基金信息：
- DOI：
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- Published：2014
- 稿件说明：
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罗汉青, 梁利平, 叶甜春. 一种基于可配置随机测试生成的多核验证方法[J]. 微电子学与计算机, 2014, 31(1): 88-91,98.

LUO Han-qing, LIANG Li-ping, YE Tian-chun. A Method Based on Configurable Random Test Generation for Multi-core Verification[J]. 2014, 31(1): 88-91.
罗汉青, 梁利平, 叶甜春. 一种基于可配置随机测试生成的多核验证方法[J]. 微电子学与计算机, 2014, 31(1): 88-91,98. DOI：

LUO Han-qing, LIANG Li-ping, YE Tian-chun. A Method Based on Configurable Random Test Generation for Multi-core Verification[J]. 2014, 31(1): 88-91. DOI：

摘要

多核设计规模和复杂度的不断提高，使功能验证变得越来越具挑战性.通过分析基于模拟仿真的多核验证方法，提出了一种基于可配置随机测试生成的多核cache一致性验证方法.该方法以随机测试生成为基础，通过配置随机生成参数来产生特定结构的多核验证指令流.此指令流的特点是，通过内存地址访问约束和多核同步操作的设置，来达成多核系统执行顺序的准确预测，进而通过自检测指令组的配置来完成自动快速结果比较.实验结果表明，该方法对多核一致性的验证是高效的.

Abstract

As multi-core designs architectural complexity increases

the challenge of verification grows dramatically.Through analyzing the methods of simulation based verification of multi-core designs

in this paper we present a new method based on configurable random test generation to verify multi-core cache coherence.Configurable random test generation is used to generate specified instruction streams by controlling generation variables.The execution sequence of the instruction stream in multi-core design can be predicted exactly by using memory address accessing constraints and synchronization operation.Further more

the self-checking instruction groups are used to check the simulation results automatically.The experiment result shows that our method is efficient.

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