Design of Low-power SAR ADC with Hybrid Encoding DAC

YANG Ming; ZHAO Yiqiang; XIA Fan

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Design of Low-power SAR ADC with Hybrid Encoding DAC

更新时间：2026-09-04

- Design of Low-power SAR ADC with Hybrid Encoding DAC
- Vol. 30, Issue 7, Pages: 91-94(2013)
- 作者机构：
  
  天津大学电子信息工程学院,天津,300072
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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杨明, 赵毅强, 夏璠. 基于混合编码DAC的低功耗SAR ADC设计[J]. 微电子学与计算机, 2013, 30(7): 91-94.

YANG Ming, ZHAO Yiqiang, XIA Fan. Design of Low-power SAR ADC with Hybrid Encoding DAC[J]. 2013, 30(7): 91-94.
杨明, 赵毅强, 夏璠. 基于混合编码DAC的低功耗SAR ADC设计[J]. 微电子学与计算机, 2013, 30(7): 91-94. DOI：

YANG Ming, ZHAO Yiqiang, XIA Fan. Design of Low-power SAR ADC with Hybrid Encoding DAC[J]. 2013, 30(7): 91-94. DOI：

摘要

设计了一种基于混合编码DAC的低功耗SAR ADC.其分段电容DAC采用混合编码，减小了短时脉冲波形干扰的影响；为降低DAC寄生效应和电容阵列失配误差的影响，在DAC和比较器的版图设计中考虑了一些匹配技术.采用GF(Global Foundry)0.35μm CMOS工艺流片验证，该ADC在500 KSPS的速度下其INL在-0.6~0.4 LSB区间范围内，DNL在-0.2~0.7 LSB区间范围内，SNDR为54.13 dB，有效位为8.7位.整个电路的功耗为537.9μW.

Abstract

A low-power successive approximation register analog -to -digital converter with hybrid encoding DAC is proposed in this paper.To decrease the glitch of the charge redistributed DAC

the split-capacitor DAC adopt the hybrid code.To increase the matching accuracy and reduce the influence of parasitic effect of DAC

some matching techniques are adopted in the layout design of the proposed DAC and capacitor.The SAR ADC is fabricated and verified in GF(Global Foundry) 0.35 μm CMOS process.The measurement results have shown that at 500 KSPS

the INL and DNL are -0.6~0.4 LSB and -0.2~0.7 LSB

respectively

the SNDR is 54.13 dB and the ENOB is 8.7 bits.The total circuit consumption is 537.9 μW.

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