Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit

SUN Zhen-ya; XU Shuang-heng; CHEN Hua; SUI Zhi-ling; YAN Xiao-yan

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Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit

更新时间：2026-09-04

- Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit
- Vol. 30, Issue 5, Pages: 112-116(2013)
- 作者机构：
  
  电子科技大学电子薄膜与集成器件国家重点实验室机构,四川,成都,610054
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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孙振亚, 徐双恒, 陈华, 眭志凌, 闫小艳. 一种12位100MSPS采样保持电路的设计[J]. 微电子学与计算机, 2013, 30(5): 112-116.

SUN Zhen-ya, XU Shuang-heng, CHEN Hua, et al. Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit[J]. 2013, 30(5): 112-116.
孙振亚, 徐双恒, 陈华, 眭志凌, 闫小艳. 一种12位100MSPS采样保持电路的设计[J]. 微电子学与计算机, 2013, 30(5): 112-116. DOI：

SUN Zhen-ya, XU Shuang-heng, CHEN Hua, et al. Design of a 12-bit 1000MSPS CMOS Sample and Hold Circuit[J]. 2013, 30(5): 112-116. DOI：

摘要

基于0.13m/3.3V CMOS工艺

设计了一种用于12bit 100MSPS Pipeline ADC的采样保持(S/H)电路.采用具有高线性度双边对称的无馈通自举采样开关

获得高增益、宽带宽的跨导前馈补偿共源共栅两级全差分跨导放大器

以及能显著降低增益误差的相关双采样S/H拓扑结构来搭建S/H电路.仿真结果表明:当在11.27MHz的输入信号

111MHz的采样信号下

该S/H电路无杂散动态范围(SFDR)86.4dB

功耗为32mW.

Abstract

A 12bit 100 MSPS pipelined analog--to digital converter (ADC) sample and hold circuit is designed based 0. 13m/3. 3V CMOS process. In this circuit

a high linearity Double Side Symmetrical No Feed Through (DSSNFT) bootstrapped switch

a high gain wide bandwidth Cascode Transconductance Feed Forward (CTFF) compensation two-stage fully differential OTA and a low gain--error correlated double sampling S/H topology structure are used to build S/H circuit. The simulation results show that SFDR can reach 86. 4dB with input signal 11.27MHz and sample signal 111MHz. Power consumption is about 32mW at a 3.3V supply.

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