FPGA-based ROHC Hardware Decompressor Design

SUN Yu-hao; ZHANG Sheng-bing

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FPGA-based ROHC Hardware Decompressor Design

更新时间：2026-09-04

- FPGA-based ROHC Hardware Decompressor Design
- Vol. 30, Issue 8, Pages: 112-115(2013)
- 作者机构：
  
  西北工业大学计算机学院,陕西,西安,710072
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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孙宇豪, 张盛兵. 基于FPGA的ROHC硬件解压器设计[J]. 微电子学与计算机, 2013, 30(8): 112-115.

SUN Yu-hao, ZHANG Sheng-bing. FPGA-based ROHC Hardware Decompressor Design[J]. 2013, 30(8): 112-115.
孙宇豪, 张盛兵. 基于FPGA的ROHC硬件解压器设计[J]. 微电子学与计算机, 2013, 30(8): 112-115. DOI：

SUN Yu-hao, ZHANG Sheng-bing. FPGA-based ROHC Hardware Decompressor Design[J]. 2013, 30(8): 112-115. DOI：

摘要

鲁棒性头压缩算法（ROHC）是一种工作在无线链接环境下，并旨在同时提供具有高压缩效率和高可靠性的的压缩方案。介绍了 RHOC 硬件解压器的实现框架，并详细给出了 ROHC 单向工作模式下硬件解压器的 FPGA实现。运行结果显示 ROHC 报头压缩算法可以将40字节 RTP/IPV4/UDP 数据包压缩至到3~4个字节并在解压缩端实现有效解压缩。

Abstract

Robust Header Compression (ROHC) is a compression scheme aims at providing a compression scheme that has high compression efficiency and high robustness when used wireless links.In this paper

we introduce the basic concept and technology of RHOC and give the architecture of RHOC hardware decompressor which works under U mode.The decompressor is implemented on FPGA.The design of the decompressor is present in this essay also.It can work effectively

and decompress the packet such as IR

IR-DYN and UO-0/UO-1/UO-2 correctly.The performance of ROHC hardware accelerator which includes compressor and decompressor is evaluated through simulation.The result shows that the ROHC hardware compressor can compress the 40 bytes IPV4/UDP/RTP packet to 3~4 bytes

and decompress effectively by the decompressor.

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