BIST Circuit Design for Network-on-chip Memory

XU Chuan-pei; TAO Yi; WU Yu-long

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BIST Circuit Design for Network-on-chip Memory

更新时间：2026-09-04

- BIST Circuit Design for Network-on-chip Memory
- Vol. 30, Issue 10, Pages: 105-109(2013)
- 作者机构：
  
  桂林电子科技大学电子工程与自动化学院,广西,桂林,541004
- 作者简介：
- 基金信息：
- DOI：
  CLC：
- Published：2013
- 稿件说明：
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许川佩, 陶意, 吴玉龙. 片上网络存储器的BIST电路设计[J]. 微电子学与计算机, 2013, 30(10): 105-109,113.

XU Chuan-pei, TAO Yi, WU Yu-long. BIST Circuit Design for Network-on-chip Memory[J]. 2013, 30(10): 105-109.
许川佩, 陶意, 吴玉龙. 片上网络存储器的BIST电路设计[J]. 微电子学与计算机, 2013, 30(10): 105-109,113. DOI：

XU Chuan-pei, TAO Yi, WU Yu-long. BIST Circuit Design for Network-on-chip Memory[J]. 2013, 30(10): 105-109. DOI：

摘要

片上网络(Network-on-Chip

NoC)作为解决片上系统存在的问题而提出的一种解决方案

正受到越来越多的关注

测试技术是NoC设计工作的重要组成部分。该设计针对NoC系统中SRAM存储器模块

研究了SRAM的故障模型

建立了片上网络通信架构的功能模型

复用片上网络作为测试存取路径

设计完成了基于M arch C+算法的BIST电路设计。该方案采用Verilog语言完成设计

并且在基于FPGA的NoC系统平台上实现了对SRAM的测试。实验结果表明

在面积开销增加较小的情况下

该方法具有较高的故障覆盖率。

Abstract

Network-on-chip(Network-on-chip

NoC) as a solution to solve the problems of System-on-chip

the test technology based on network-on-chip has caused more and more attention.Test technology of NoC is one of the important parts.In this method

we research on fault model of SRAM memory and establish the functional model of NoCs communication architecture

design the BIST circuit reusing network-on-chip as TAM (Test Access Mechanism)to test SRAM memory based on March C + algorithm.This method was designed by verilog language

and implement the test in NoC system platform based on FPGA.Experiment results show that this method has a high fault coverage with the small increase in area overhead.

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