In order to design the performance parameter of high reliability standard cell library

it need to research the related performance parameter of inverter which is the basic unit in a standard cell library.Balancing delay characteristics

noise margins and power consumption etc factors

firstly decide the PMOS-to-NMOS ratio of the inverter

then size the specific transistor.So a suit of scheme to size the minimum inverter is presented.Finally building a set of logic circuit according to logic effort

simulation results show that the inverter has the great advantage of performance and power consumption.All of these provide some reference for sizing the cells of the deep sub-micron and nanoscale standard cell library.