To accelerateverification speed of scheduling algorithm in heterogeneous architecture and reduce time consumption and verification complexity

this design utilizes software simulation technique to build a multi-task parallel execution model for heterogeneous architecture.This technique uses ERT matrix

communication factor matrix

output array and machine time array to simulate different hardware environment.A parallel model is implemented via serious languagewhich has the function of data forwarding and out-of-order scheduling.No system API is referred considering portability in the designing process.