A Low Power DFT Technology Based on EDT

CHEN Shou-zhi; WANG Xiao-li; ZHANG Xian-rao

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A Low Power DFT Technology Based on EDT

更新时间：2026-09-04

- A Low Power DFT Technology Based on EDT
- Vol. 30, Issue 11, Pages: 159-164(2013)
- 作者机构：
  
  1. 西安交通大学电信学院,陕西,西安,710049
  2. 西安交通大学理学院,陕西,西安,710049
- 作者简介：
- 基金信息：
- DOI：
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- Published：2013
- 稿件说明：
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陈首智, 王小力, 张先娆. 一种基于EDT的低功耗可测性设计技术研究[J]. 微电子学与计算机, 2013, 30(11): 159-164.

CHEN Shou-zhi, WANG Xiao-li, ZHANG Xian-rao. A Low Power DFT Technology Based on EDT[J]. 2013, 30(11): 159-164.
陈首智, 王小力, 张先娆. 一种基于EDT的低功耗可测性设计技术研究[J]. 微电子学与计算机, 2013, 30(11): 159-164. DOI：

CHEN Shou-zhi, WANG Xiao-li, ZHANG Xian-rao. A Low Power DFT Technology Based on EDT[J]. 2013, 30(11): 159-164. DOI：

摘要

本文介绍了一种基于ED T的低功耗可测性设计技术，并提出该技术在设置功耗阈值时的优化方案.该低功耗可测性设计技术通过对测试图形进行0填充，使电路在测试过程中的WSA得到有效降低，从31.55%优化到了25.12%.通过设置功耗阈值，降低了测试功耗峰值，实验电路的LST最大值从49.76%优化到21.21%，RST 最大值从45.73%优化到25.00%，并使WSA和SET的最大值得到相应优化.理论研究和实验表明，缩短扫描链长度能够有效提高设置功耗阈值时的测试覆盖率.

Abstract

This paper presents a low power DFT technology based on EDT

and introduces an optimization method when setting power threshold.This low power DFT technology has the ability to reduce WSA during testing by filling 0 to test patterns

which optimizes WSA from 31.55% to 25.12%.Otherwise

setting power threshold can reduce peak testing power

which optimizes LST to 49.76% to 21.21%

RST from 45.73% to 25.00%.Coverage drop

caused by power threshold

could be improved by reducing the scan chains length.

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